Memory devices and methods of operating the same

ABSTRACT

A memory device includes a memory cell. The memory cell includes: a bipolar memory element and a bidirectional switching element. The bidirectional switching element is connected to ends of the bipolar memory element, and has a bidirectional switching characteristic. The bidirectional switching element includes: a first switching element and a second switching element. The first switching element is connected to a first end of the bipolar memory element and has a first switching direction. The second switching element is connected to a second end of the bipolar memory element and has a second switching direction. The second switching direction is opposite to the first switching direction.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority under 35 U.S.C. §119 to Korean PatentApplication No. 10-2009-0131291, filed on Dec. 24, 2009, in the KoreanIntellectual Property Office, the disclosure of which is incorporatedherein in its entirety by reference.

BACKGROUND

1. Field

Example embodiments relate to memory devices and methods of operatingthe same.

2. Description of the Related Art

A resistance memory device is an example of a non-volatile memorydevice. The resistive memory device stores data using a variableresistance characteristic of a material such as a transition metaloxide. A transition metal oxide has a resistance that significantlychanges at a particular voltage level. In other words, the resistance ofthe variable resistance material decreases when a voltage exceeding aset voltage is applied thereto. This state is referred to as an ONstate. Furthermore, when a voltage exceeding a reset voltage is appliedto the variable resistance material, the resistance thereof increases.This state is referred to as an OFF state.

SUMMARY

Example embodiments provide memory devices having bipolarcharacteristics and methods of operating the same. At least some exampleembodiments provide memory devices having bipolar characteristics andmethods of operating the same.

Additional aspects will be set forth in part in the description whichfollows, and in part, will be apparent from the description, or may belearned by practice of example embodiments.

At least one example embodiment provides a memory device including amemory cell. The memory cell includes: a bipolar memory element; and abidirectional switching element. The bidirectional switching element isconnected to ends of the bipolar memory element, and has a bidirectionalswitching characteristic.

At least one other example embodiment provides a memory device includinga memory cell. According to at least this example embodiment, the memorycell includes: a bipolar memory element; a first switching elementconnected to an end of the bipolar memory element and having a firstswitching direction; and a second switching element connected to anotherend of the bipolar memory element and having a second switchingdirection. The second switching direction is opposite to the firstswitching direction.

At least one example embodiment provides a memory card. The memory cardincludes: a controller and a memory. The memory is configured toexchange data with the controller according to commands from thecontroller. In one example, the memory includes a memory device, whichfurther includes a memory cell having a bipolar memory element and abidirectional switching element. The bidirectional switching element isconnected to ends of the bipolar memory element, and has a bidirectionalswitching characteristic.

At least one other example embodiment provides an electronic device. Theelectronic device includes: a processor configured to execute a programand control the electronic device; an input/output device configured toinput/output data to/from the electronic device; and a memory configuredto store at least one of codes and programs for operating the processor.The processor, the input/output device and the memory are configured toexchange data via a bus. In one example, the memory includes a memorydevice, which further includes a memory cell having a bipolar memoryelement and a bidirectional switching element. The bidirectionalswitching element is connected to ends of the bipolar memory element,and has a bidirectional switching characteristic.

According to at least some example embodiments, the first and secondswitching elements may be Schottky diodes. The first switching elementmay include a first semiconductor layer. The second switching elementmay include a second semiconductor layer. The first and secondsemiconductor layers may contact (e.g., directly contact) the bipolarmemory element. The bipolar memory element and the first and secondsemiconductor layers may be oxide layers. An oxygen concentration of thebipolar memory element may be lower than oxygen concentrations of thefirst and second semiconductor layers.

According to at least some other example embodiments, the first andsecond switching elements may be pn diodes. In these examples, the firstswitching element may include a first semiconductor layer, and thesecond switching element may include a second semiconductor layer. Thefirst and second semiconductor layers may contact the bipolar memoryelement. A conductive region may be formed in a portion of each of thefirst and second semiconductor layers contacting the bipolar memoryelement.

The first and second semiconductor layers may be n-type oxide layers,and the conductive region may have a lower oxygen concentration than theresidue regions of the first and second semiconductor layers.Alternatively, the first and second semiconductor layers may be p-typeoxide layers, and the conductive region may have a higher oxygenconcentration than the residue regions of the first and secondsemiconductor layers.

The bipolar memory element may be (or constitute) a portion of the firstand second switching elements.

According to at least some example embodiments, the memory cell mayinclude a first semiconductor layer having a first conduction type, andsecond and third semiconductor layers having a second conduction typedisposed on both ends of the first semiconductor layer. The firstsemiconductor layer may be the bipolar memory element, the firstsemiconductor layer and the second semiconductor layer may form thefirst switching element; and the first semiconductor layer and the thirdsemiconductor layer may form the second switching element.

According to at least some example embodiments, the bipolar memoryelement may include an oxide resistor. The oxide resistor may include atleast one material selected from the group consisting of or including:Ti oxide, Ni oxide, Cu oxide, Co oxide, Hf oxide, Zr oxide, Zn oxide, Woxide, Nb oxide, TiNi oxide, LiNi oxide, Al oxide, InZn oxide, V oxide,SrZr oxide, SrTi oxide, Cr oxide, Fe oxide, Ta oxide, and PCMO(PrCaMnO).

Each of the first and second switching elements may include an oxidesemiconductor. The oxide semiconductor may include an oxide of the sameor a different group as the oxide resistor.

The oxygen concentration of at least a portion of the bipolar memoryelement may be different from the oxygen concentration of at least aportion of the first and second switching elements.

A doping condition of at least a portion of the bipolar memory elementmay be different from a doping condition of at least a portion of thefirst and second switching elements.

The bi-directional switching element may directly contact the ends ofthe bipolar memory element. In one example, the first and secondswitching elements may directly contact ends of the bipolar memoryelement.

The memory cell may be an oxide unit.

According to at least some example embodiments, the memory device mayfurther include: a plurality of first electrodes having a wire shape,which are disposed in parallel with each other; and a plurality ofsecond electrodes having a wire shape, which are disposed in parallelwith each other. The memory cell may be disposed at each of theintersections of the first and second electrodes.

The memory cell may be a first memory cell, and the memory device mayfurther include a plurality of third electrodes, which cross the secondelectrodes; and a second memory cell disposed at each of theintersections of the second and third electrodes. The plurality of thirdelectrodes may have a wire shape, and be in parallel with each other.

The second memory cell and the first memory cell may have a same orsubstantially the same structure.

Alternatively, the second memory cell may have a modified structure fromthe first memory cell in which the switching directions of first andsecond switching elements are inversed.

According to at least some example embodiments, an intermediateelectrode is not disposed between a memory layer and a switching elementto electrically connect the memory layer to the switching element.

BRIEF DESCRIPTION OF THE DRAWINGS

These and/or other aspects will become apparent and more readilyappreciated from the following description of example embodiments, takenin conjunction with the accompanying drawings of which:

FIG. 1 is a cross-sectional view of a memory cell according to anexample embodiment;

FIGS. 2A and 2B are circuit diagrams corresponding to the memory cell ofFIG. 1;

FIG. 3 is a cross-sectional view of an example embodiment of the memorycell of FIG. 1 in which the switching elements are Schottky diodes;

FIG. 4 is an energy band diagram for a switching element that is used ina memory cell according to an example embodiment;

FIG. 5 is a graph showing voltage-current characteristics of a switchingelement corresponding to the energy band diagram shown in FIG. 4;

FIG. 6 is a graph showing voltage-current characteristics of a bipolarmemory element according to an example embodiment;

FIG. 7 is a graph showing voltage-current characteristics of a memorycell according to an example embodiment;

FIGS. 8 and 9 are cross-sectional views of an example embodiment of thememory cell of FIG. 1 in which the switching elements are pn diodes;

FIG. 10 is a cross-sectional view of a memory cell according to anotherexample embodiment;

FIGS. 11 and 12 are graphs showing voltage-current characteristics ofmemory cells according to example embodiments;

FIG. 13 is a perspective view of a memory device according to an exampleembodiment;

FIGS. 14A and 14B are circuit diagrams of memory devices according toexample embodiments;

FIG. 15 is a schematic diagram illustrating a memory card according toan example embodiment; and

FIG. 16 is a block diagram illustrating an electronic system accordingto an example embodiment.

DETAILED DESCRIPTION

Various example embodiments will now be described more fully withreference to the accompanying drawings in which some example embodimentsare shown.

It will be understood that when an element is referred to as being“connected” or “coupled” to another element, it can be directlyconnected or coupled to the other element or intervening elements may bepresent. In contrast, when an element is referred to as being “directlyconnected” or “directly coupled” to another element, there are nointervening elements present. As used herein the term “and/or” includesany and all combinations of one or more of the associated listed items.

It will be understood that, although the terms “first,” “second,” etc.may be used herein to describe various elements, components, regions,layers and/or sections, these elements, components, regions, layersand/or sections should not be limited by these terms. These terms areonly used to distinguish one element, component, region, layer orsection from another element, component, region, layer or section. Thus,a first element, component, region, layer or section discussed belowcould be termed a second element, component, region, layer or sectionwithout departing from the teachings of example embodiments.

Spatially relative terms, such as “beneath,” “below,” “lower,” “above,”“upper” and the like, may be used herein for ease of description todescribe one element or feature's relationship to another element(s) orfeature(s) as illustrated in the figures. It will be understood that thespatially relative terms are intended to encompass differentorientations of the device in use or operation in addition to theorientation depicted in the figures. For example, if the device in thefigures is turned over, elements described as “below” or “beneath” otherelements or features would then be oriented “above” the other elementsor features. Thus, the example term “below” can encompass both anorientation of above and below. The device may be otherwise oriented(rotated 90 degrees or at other orientations) and the spatially relativedescriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of exampleembodiments. As used herein, the singular forms “a,” “an” and “the” areintended to include the plural forms as well unless the context clearlyindicates otherwise. It will be further understood that the terms“comprises” and/or “comprising,” when used in this specification,specify the presence of stated features, integers, steps, operations,elements, and/or components, but do not preclude the presence oraddition of one or more other features, integers, steps, operations,elements, components, and/or groups thereof.

Example embodiments are described herein with reference to schematiccross-sectional illustrations of example embodiments. Variations fromthe shapes of the illustrations as a result, for example, ofmanufacturing techniques and/or tolerances, are to be expected. Thus,example embodiments should not be construed as limited to the particularshapes of regions illustrated herein, but are to include deviations inshapes that result, for example, from manufacturing. For example, animplanted region illustrated as a rectangle will, typically, haverounded or curved features and/or a gradient of implant concentration atits edges rather than a binary change from the implanted to anon-implanted region. Likewise, a buried region formed by implantationmay result in some implantation in the region between the buried regionand the surface through which the implantation takes place. Thus, theregions illustrated in the figures are schematic in nature and theirshapes are not intended to illustrate the actual shape of a region of adevice and are not intended to limit the scope of example embodiments.

Unless otherwise defined, all terms (including technical and scientificterms) used herein have the same meaning as commonly understood by oneof ordinary skill in the art to which example embodiments belong. Itwill be further understood that terms, such as those defined incommonly-used dictionaries, should be interpreted as having a meaningthat is consistent with their meaning in the context of the relevant artand will not be interpreted in an idealized or overly formal senseunless expressly so defined herein.

In the drawings, the thicknesses of layers and regions are exaggeratedfor clarity. Like reference numerals in the drawings denote likeelements.

Hereinafter, memory devices according to example embodiments and methodsof operating the same will be described in more detail with reference tothe attached drawings. Throughout the detailed description section ofthe present application, like reference numerals denote like elements.

FIG. 1 is a cross-sectional view of a memory cell MC1 of a memory deviceaccording to an example embodiment.

Referring to FIG. 1, the memory cell MC1 includes a bipolar memoryelement M1 and first and second switching elements S1 and S2. The firstand second switching elements S1 and S2 contact opposite ends of thebipolar memory element M1. More specifically, in the example embodimentshown in FIG. 1, the first and second switching elements S1 and S2contact top and bottom surfaces, respectively, of the bipolar memoryelement M1.

In FIG. 1, each of the first and second switching elements S1 and S2 areone-way switching elements, and the switching directions of the firstand second switching elements S1 and S2 are opposite to each other.Accordingly, a combination of the first switching element S1 and thesecond switching element S2 is referred to as a “two-way switchingelement” or a “bidirectional switching element.”

Still referring to FIG. 1, a first electrode E1 is connected to thefirst switching element S1, and a second electrode E2 is connected tothe second switching element S2. In this example, the first electrode E1contacts a bottom surface of the first switching element S1, whereas thesecond electrode E2 contacts a top surface of the second switchingelement S2. The first electrode E1 may be a portion of the firstswitching element S1, and the second electrode E2 may be a portion ofthe second switching element S2.

The bipolar memory element M1 may be a resistive memory element. In thisregard, the bipolar memory element M1 may include an oxide resistor. Theoxide resistor may be a metal oxide resistor, and may also be a variableresistor having a resistance that changes according to an appliedvoltage. For example, the bipolar memory element M1 may include at leastone material selected from the group consisting of or including:titanium (Ti) oxide, nickel (Ni) oxide, copper (Cu) oxide, cobalt (Co)oxide, hafnium (Hf) oxide, zirconium (Zr) oxide, zinc (Zn) oxide,tungsten (W) oxide, niobium (Nb) oxide, titanium nickel (TiNi) oxide,lithium nickel (LiNi) oxide, aluminum (Al) oxide, indium zinc (InZn)oxide, vanadium (V) oxide, strontium zirconium (SrZr) oxide, strontiumtitanium (SrTi) oxide, chromium (Cr) oxide, iron (Fe) oxide, tantalum(Ta) oxide, a combination thereof or the like. These materials may havea unipolar or bipolar characteristic according to formation conditions.The example embodiment shown in FIG. 1, however, is described withregard to materials having a bipolar characteristic are used.

The material of the bipolar memory element M1 is not limited to theabove listed materials. Rather, the bipolar memory element M1 mayinclude other materials such as PrCaMnO (PCMO) or the like having abipolar characteristic.

Still referring to FIG. 1, each of the first and second switchingelements S1 and S2 may be, for example, a diode or a threshold switchingdevice. The diode may be, for example, a Schottky diode or a pn diode.Each of the first and second switching elements S1 and S2 may include anoxide semiconductor. In more detail, when each of the first and secondswitching elements S1 and S2 is a Schottky diode, each of the first andsecond switching elements S1 and S2 may include a semiconductor layerand a metal layer, which contact each other. The semiconductor layer maybe an oxide layer and may contact the bipolar memory element M1. In oneexample, the semiconductor layer may be interposed between the metallayer and the bipolar memory element M1. In this example, the metallayer together with the semiconductor layer forms a Schottky barrier.The metal layer may be used as corresponding first or second electrodeE1 or E2.

When the first and second switching elements S1 and S2 are pn diodes,each of the first and second switching elements S1 and S2 may include ann-type oxide semiconductor layer and a p-type oxide semiconductor layer,which contact each other. Either of the n-type oxide semiconductor layerand the p-type oxide semiconductor layer may contact the bipolar memoryelement M1.

The oxide semiconductors of the first and second switching elements S1and S2 may include an oxide of the same group as the oxide resistor ofthe bipolar memory element M1. In this case, an oxygen concentration ofat least a portion of the oxide semiconductors of the first and secondswitching elements S1 and S2 is different from an oxygen concentrationof at least a portion of the oxide resistor of the bipolar memoryelement M1. For example, the oxygen concentration of the oxide resistorof the bipolar memory element M1 may be lower than the oxygenconcentration of the oxide semiconductors of the first and secondswitching elements S1 and S2. Alternatively, a doping condition (e.g.,doping material and/or doping concentration) of at least a portion ofthe oxide semiconductors of the first and second switching elements S1and S2 may be different from a doping condition (e.g., doping materialand/or doping concentration) of at least a portion of the oxide resistorof the bipolar memory element M1.

According to at least some other example embodiments, the oxidesemiconductors of the first and second switching elements 51 and S2 mayinclude an oxide of a different group from the oxide resistor of thebipolar memory element M1.

Still referring to FIG. 1, the first and second electrodes E1 and E2 maybe formed of conventional electrode materials used in semiconductordevices, and each of the first and second electrodes E1 and E2 may havea single-layered or multi-layered structure. For example, each of thefirst and second electrodes E1 and E2 may include at least one selectedfrom the group including: platinum (Pt), gold (Au), palladium (Pd),iridium (Ir), silver (Ag), nickel (Ni), aluminum (Al), molybdenum (Mo),copper (Cu), combinations thereof or the like. The first and secondelectrodes E1 and E2 may include the same, substantially the same ordifferent material and/or may have the same, substantially the same or adifferent structure. According to example embodiments, the first andsecond electrodes E1 and E2 may or may not be portions of the first andsecond switching elements S1 and S2, respectively.

FIGS. 2A and 2B are circuit diagrams of example embodiments of thememory cell MC1 shown in FIG. 1. In the memory cell MC1 of FIGS. 2A and2B, the first and second switching elements S1 and S2 are diodes.

Referring to FIG. 2A, a switching direction (also referred to as arectification direction) of the first switching element S1 is a firstdirection d1, whereas a switching direction of a second switchingelement S2 is a second direction d2. The second direction d2 is oppositeto the first direction d1.

Referring to FIG. 2B, the switching direction of the first switchingelement S1 is the second direction d2, whereas the switching directionof the second switching element S2 is the first direction d1. Again, thefirst and second directions d1 and d2 are opposite.

FIG. 3 illustrates an example embodiment of a memory cell in which thefirst and second switching elements S1 and S2 of FIG. 1 are Schottkydiodes.

Referring to FIG. 3, a first Schottky diode SD1 is formed on a bottomsurface of the bipolar memory element M1 and a second Schottky diode SD2is formed on a top surface of the bipolar memory element M1. The firstSchottky diode SD1 includes a first semiconductor layer 1 a and a firstmetal layer 2 a sequentially disposed on the bottom surface of thebipolar memory element M1. The second Schottky diode SD2 includes asecond semiconductor layer 1 b and a second metal layer 2 b sequentiallydisposed on the top surface of the bipolar memory element M1. Each ofthe first and second semiconductor layers 1 a and 1 b may be an n-typeor p-type semiconductor layer. The first and second semiconductor layers1 a and 1 b may be the same, substantially the same or different fromeach other. In one example, each of the first and second semiconductorlayers 1 a and 1 b may be an oxide layer including an oxide of the samegroup as or a different group from the bipolar memory element M1.

In one example, if the first and second semiconductor layers 1 a and 1 bare n-type semiconductor layers, the first and second semiconductorlayers 1 a and 1 b may be TiO_(x) layers, ZnO_(x) layers, IZO layers,combinations thereof, or the like.

In another example, when the first and second semiconductor layers 1 aand 1 b are p-type semiconductor layers, the first and secondsemiconductor layers 1 a and 1 b may be NiO_(x) layers, CuO_(x) layers,combinations thereof, or the like.

Still referring to the example embodiment shown in FIG. 3, in thisexample the first and second metal layers 2 a and 2 b are metal layersthat form Schottky barriers together with the first and secondsemiconductor layers 1 a and 1 b, respectively. Each of the first andsecond metal layers 2 a and 2 b may be used as an electrode for applyinga voltage to the memory cell of FIG. 3 (e.g., corresponding to the firstand second electrodes E1 and E2 shown in FIG. 1.)

When the first and second semiconductor layers 1 a and 1 b and thebipolar memory element M1 include oxides from the same group, the oxygenconcentration of the bipolar memory element M1 may be different from theoxygen concentration of the first and second semiconductor layers 1 aand 1 b. In one example, the oxygen concentration of the bipolar memoryelement M1 is lower than the oxygen concentration of the first andsecond semiconductor layers 1 a and 1 b. In addition, the dopingcondition (e.g., doping material and/or doping concentration) of thebipolar memory element M1 may be different from the doping condition(e.g., doping material and/or doping concentration) of the first andsecond semiconductor layers 1 a and 1 b.

According to at least one other example embodiment, the first and secondsemiconductor layers 1 a and 1 b may include an oxide of a differentgroup from the bipolar memory element M1. When the Schottky diodes SD1and SD2 illustrated in FIG. 3 are used, the circuit diagram of thememory cell including the Schottky diodes SD1 and SD2 may be the same asillustrated in FIG. 2A.

In one example, the stacked structure of first metal layer 2 a/firstsemiconductor layer 1 a/bipolar memory element M1/second semiconductorlayer 1 b/second metal layer 2 b shown in FIG. 3 may be Pt/TiO_(x)(30%)/TiO_(x) (15%)/TiO_(x) (30%)/Pt. With regard to TiO_(x) (30%) andTiO_(x) (15%), the numbers in parentheses represent the percentage ofoxygen contained in a deposition gas used when a film (TiO_(x)) isdeposited. The deposition gas may be a mixed gas including oxygen (O₂)and argon (Ar), but is not limited thereto. Accordingly, the oxygenconcentration of TiO_(x) (15%) is smaller than the oxygen concentrationof TiO_(x) (30%). In this example, x in TiO_(x) (15%) may be smallerthan x in TiO_(x) (30%). The numbers in parentheses represent thepercentage of oxygen contained in a deposition gas throughout thisdescription.

FIG. 4 is an energy band diagram for a memory cell having the structureof FIG. 3 in which the bipolar memory element M1 is not included. Thatis, FIG. 4 is an energy band diagram of a structure in which the firstSchottky diode SD1 and second Schottky diode SD2 of FIG. 3 contact eachother. The first and second semiconductor layers 1 a and 1 b are TiO_(x)(30%) layers, and the first and second metal layers 2 a and 2 b are Ptlayers. In other words, FIG. 4 is an energy band diagram of thestructure of Pt/TiO_(x) (30%)/Pt. The structure of Pt/TiO_(x) (30%)corresponds to the first Schottky diode SD1, and the structure ofTiO_(x) (30%)/Pt corresponds to the second Schottky diode SD2. Referencenumeral E_(C) denotes a minimum energy level of a conduction band, andreference numeral E_(F) denotes a Fermi energy level.

Referring to FIG. 4, a first Schottky barrier B1 is formed between abottom Pt layer and a TiO_(x) (30%) layer, and a second Schottky barrierB2 is formed between a top Pt layer and a TiO_(x) (30%) layer. Thus, thebottom Pt layer and the TiO_(x) (30%) layer form a first Schottky diode,and the top Pt layer and the TiO_(x) (30%) layer form a second Schottkydiode. The first and second Schottky barriers B1 and B2 may havedifferent heights if an interface characteristic of the bottom Pt layerand the TiO_(x) (30%) layer is different from an interfacecharacteristic of the top Pt layer and the TiO_(x) (30%) layer. In atleast this example embodiment, the height of the second Schottky barrierB2 is smaller (e.g., slightly smaller) than that of the first Schottkybarrier B1. However, according to at least one other example embodiment,the heights of the first and second Schottky barriers B1 and B2 may bethe same or substantially the same.

The heights of the first and second Schottky barriers B1 and B2 may becontrolled by changing an electrode material or a semiconductor materialforming a Schottky barrier together with the electrode material in thestructure corresponding to FIG. 4; that is, the structure of Pt/TiO_(x)(30%)/Pt. For example, if an IZO layer is used instead of the TiO_(x)(30%) layer, the heights of the first and second Schottky barriers B1and B2 may be changed. Because the conduction band offset occurringbetween TiO_(x) and Pt is about 1.54 eV and the conduction band offsetoccurring between IZO and Pt is about 0.24 eV, the Schottky barrierbetween IZO and Pt is lower than the Schottky barrier of TiO_(x) and Pt.As described above, characteristics of a Schottky diode may becontrolled by changing materials for forming a semiconductor layer and ametal layer, which form a Schottky diode.

FIG. 5 is a graph showing voltage-current characteristics of theabove-described Pt/TiO_(x) (30%)/Pt structure. In FIG. 5, the x axisrepresents a voltage (V) applied to the top Pt layer. In this regard,about 0 V is applied to the bottom Pt layer.

Referring to FIG. 5, when the voltage applied to the top Pt layer isincreased in a positive (+) direction from about 0 V, the switchingelement turns on when the voltage is about +1.5 V. That is, the firstSchottky diode (e.g., a diode including the bottom Pt layer and theTiO_(x) (30%) layer) turns on. In addition, when the voltage applied tothe top Pt layer is increased in a negative (−) direction from about 0V, a switching element turns on when the voltage is about −0.5 V. Thatis, the second Schottky diode (e.g., a diode including the TiO_(x) (30%)layer and the top Pt layer) turns on. When a positive (+) voltage isapplied to the top Pt layer, a Schottky barrier between the bottom Ptlayer and the TiO_(x) (30%) layer (e.g., the first Schottky barrier B1of FIG. 4) is a relatively effective barrier, and when a negative (−)voltage is applied to the top Pt layer, a Schottky barrier between thetop Pt layer and the TiO_(x) (30%) layer (e.g., the second Schottkybarrier B2 of FIG. 4) is a relatively effective barrier. Thus, theresults of FIG. 5 show that the structure of Pt/TiO_(x) (30%)/Ptstructure has a two-way switching characteristic.

FIG. 6 shows voltage-current characteristics of a Pt/TiO_(x) (15%)/Ptstructure. In this regard, the TiO_(x) (15%) layer is a bipolar memoryelement.

Referring to FIG. 6, the bipolar memory element, which is a TiO_(x)(15%) layer, has a bipolar characteristic. First and second graphs G1and G2 located in a positive (+) voltage range show characteristics of abipolar memory element in OFF and ON states, respectively. Third andfourth graphs G3 and G4 located in a negative (−) voltage range showcharacteristics of a bipolar memory element in ON and OFF states,respectively.

Before programming, when a voltage is increased in the positive (+)direction from about 0 V, the voltage-current characteristic follows thefirst graph G1 and when a voltage greater than or equal to a given setvoltage is applied, the voltage-current characteristic follows thesecond graph G2. In this state, the voltage-current characteristicfollows the third graph G3 when the voltage is increased in the negative(−) direction, and the voltage-current characteristic follows the fourthgraph G4 when a voltage greater than or equal to a given reset voltageis applied. Moreover, in this state, the voltage-current characteristicfollows the first graph G1 when the voltage is increased in the positive(+) direction.

As described above, setting and resetting of the bipolar memory elementis performed using positive (+) voltages and negative (−) voltages. Theconcept of the setting and resetting may be altered.

FIG. 7 shows voltage-current characteristics of the Pt/TiO_(x)(30%)/TiO_(x) (15%)/TiO_(x) (30%)/Pt structure described above. As shownby the first through fourth graphs G1′ through G4′ in FIG. 7, thestructure of Pt/TiO_(x) (30%)/TiO_(x) (15%)/TiO_(x) (30%)/Pt showsswitching (or rectification) characteristics in two-ways based on about0 V and memory characteristics. Such results are similar to thecombination of the results of FIGS. 5 and 6. In FIG. 7, setting andresetting is performed using the positive (+) voltage and the negative(−) voltage, and such a hysteresis curve shows a bipolar characteristic.

As described above, a memory cell having a bipolar memory function and atwo-way switching function may be formed by forming the first and secondsemiconductor layers 1 a and 1 b and the bipolar memory element M1 usingoxides of the same group, wherein the oxygen concentration of the firstand second semiconductor layers 1 a and 1 b is different from the oxygenconcentration of the bipolar memory element M1. In this regard, thestack structure of the first semiconductor layer 1 a, the bipolar memoryelement M1, and the second semiconductor layer 1 b may form an oxideunit in which the oxygen concentration changes in a height direction.The first semiconductor layer 1 a, the bipolar memory element M1, andthe second semiconductor layer 1 b may be deposited in-situ, and may bepatterned at least once using a single mask.

Conventionally, an intermediate electrode is disposed between a memorylayer and a switching element to electrically connect the memory layerto the switching element. According to at least this example embodiment,however, the intermediate electrode is omitted, and the bipolar memoryelement M1 directly contacts the switching elements S1 and S2. Memoryand switching functions are still obtained even though the bipolarmemory element M1 directly contacts the switching elements S1 and S2. Inorder to embody memory and switching functions through direct contact,at least portions of the bipolar memory element M1 and switchingelements S1 and S2 are formed of oxides with different oxygenconcentrations. In this regard, even when the bipolar memory element M1directly contacts the switching elements S1 and S2, normal memory andswitching characteristics may be obtained. As described above, variousdesirable effects may be obtained even when an intermediate electrode isnot used.

When the intermediate electrode is used as in conventional memorydevices, it is relatively difficult to balance the characteristics of amemory element and a switching element because the characteristics ofthe memory element and the switching element are independent. Suchdifficulty may become relatively serious as devices becomes moreintegrated. For example, in more highly integrated devices, a forwardcurrent density of the switching element is increased by increasing asize (width) of the switching element to obtain a normal resistancechange characteristic of a memory layer, thereby enabling programming ofthe memory layer. However, when the size (width) of the switchingelement is increased, scaling down a device and the manufacturingprocess becomes relatively difficult.

However, according to at least some example embodiments, the switchingelement may have fewer or no requirements, to be satisfied becausememory and switching functions are obtained by directly contacting thememory element and the switching element. Accordingly, scaling down ofthe switching element may be easier, and a memory device may be morehighly integrated. In addition, the height of the memory cell may bereduced and the manufacturing process may be simplified because theintermediate electrode need not be formed.

FIG. 8 illustrates an example embodiment in which the first and secondswitching elements 51 and S2 of FIG. 1 are pn diodes.

Referring to FIG. 8, a first pn diode PN1 is disposed on the bottomsurface of the bipolar memory element M1, and a second pn diode PN2 isdisposed on the top surface of the bipolar memory element M1. The firstpn diode PN1 includes a first semiconductor layer 10 a and a secondsemiconductor layer 20 a, which are sequentially disposed on the bottomsurface of the bipolar memory element M1. The second pn diode PN2includes a third semiconductor layer 10 b and the fourth semiconductorlayer 20 b, which are sequentially disposed on the top surface of thebipolar memory element M1.

The first and third semiconductor layers 10 a and 10 b, which contactthe bipolar memory element M1, may be the same type of (first conductiontype) semiconductor layers. The second and fourth semiconductor layers20 a and 20 b, which are separated from the bipolar memory element M1,may be a different type (second conduction-type) from that of the firstand third semiconductor layers 10 a and 10 b. The first and thirdsemiconductor layers 10 a and 10 b may be n-type semiconductor layers,whereas the second and fourth semiconductor layers 20 a and 20 b may bep-type semiconductor layers, or vice versa.

The semiconductor layers 10 a, 10 b, 20 a, and 20 b may be oxide layers.In this case, the semiconductor layers 10 a, 10 b, 20 a, and 20 b mayinclude an oxide of the same group as or a different group from thebipolar memory element M1. For example, among the oxide layers, a p-typeoxide layer may be a CuO_(x) layer or a NiO_(x) layer, and the n-typeoxide layer may be an IZO layer, a TiO_(x) layer, or a ZnO_(x) layer. Ina p-type oxide layer such as a CuO_(x) layer, metal vacancies may beformed naturally, and thus, holes may act as carriers. In an n-typeoxide layer such as an IZO layer, oxygen vacancies may be formednaturally, and thus, electrons may act as carriers. Amorphous oxidelayers, which are more easily formed at room temperature, may be used toform the first and second pn diodes PN1 and PN2. In addition, the firstand second pn diodes PN1 and PN2 may be formed using crystalline oxidelayers. In the case of a silicon diode, the manufacturing process may beperformed at a temperature as high as about 800° C. As a result, only aselected substrate may be used and various problems may occur due to therelatively high temperature. Thus, there are various advantages when thefirst and second pn diodes PN1 and PN2 are manufactured using oxidelayers, which are formed more easily at room temperature. However, thematerial for forming the first and second pn diode PN1 and PN2 is notlimited to oxides. Rather, the first and second pn diodes PN1 and PN2may also include non-oxides.

The bipolar memory element M1 may include an oxide of the same group asthe first and third semiconductor layers 10 a and 10 b, which contactthe bipolar memory element M1. In this case, the oxygen concentration ofat least a portion of the bipolar memory element M1 may be differentfrom the oxygen concentration of at least a portion of the first andthird semiconductor layers 10 a and 10 b. In addition; the dopingcondition (e.g., doping material and/or doping concentration) of atleast a portion of the bipolar memory element M1 may be different fromthe doping condition (e.g., doping material and/or doping concentration)of at least a portion of the first and third semiconductor layers 10 aand 10 b. According to at least one other example embodiment, an oxideof the bipolar memory element M1 and oxides of the first and thirdsemiconductor layers 10 a and 10 b may be of a different group from eachother.

Referring back to FIG. 8, a first electrode E1 is disposed on a bottomsurface of the second semiconductor layer 20 a, and a second electrodeE2 is disposed on a top surface of the fourth semiconductor layer 20 b.The first electrode E1 may be formed of a metal that makes ohmic contactwith the second semiconductor layer 20 a. The second electrode E2 may beformed of a metal that makes ohmic contact with the fourth semiconductorlayer 20 b.

When using the first and second pn diodes PN1 and PN2 illustrated inFIG. 8, the circuit diagram of the memory cell may be the same asillustrated in FIG. 2A or FIG. 2B.

On the one hand, in FIG. 8, when the first and third semiconductorlayers 10 a and 10 b are n-type semiconductor layers and the second andfourth semiconductor layers 20 a and 20 b are p-type semiconductorlayers, the circuit diagram of the memory cell may be the same asillustrated in FIG. 2A.

On the other hand, in FIG. 8, when the first and third semiconductorlayers 10 a and 10 b are p-type semiconductor layers and the second andfourth semiconductor layers 20 a and 20 b are n-type semiconductorlayers, the circuit diagram of the memory cell may be the same asillustrated in FIG. 2B.

FIG. 9 is a cross-sectional view of a memory cell according to anotherexample embodiment in which the first and second switching elements S1and S2 are pn diodes. In FIG. 9, the reference numerals 10 a′, 20 a′, 10b′, and 20 b′ denote first through fourth semiconductor layers,respectively, and PN1′ and PN2′ denote first and second pn diodes. Thefirst and third semiconductor layers 10 a′ and 10 b′ are firstconduction-type semiconductors, whereas the second and fourthsemiconductor layers 20 a′ and 20 b′ are second conduction-typesemiconductors.

Referring to FIG. 9, the first semiconductor layer 10 a′ may include aregion having relatively high electric conductivity (or conductiveregion, which is referred to hereinafter as a first region R1) at aninterface between the first semiconductor layer 10 a′ and the bipolarmemory element M1. A residue region of the first semiconductor layer 10a′ (referred to hereinafter as a second region R2), other than the firstregion R1, has a semiconductor characteristic.

Like the first semiconductor layer 10 a′, the third semiconductor layer10 b′ may have a region having relatively high electric conductivity (orconductive region, which is hereinafter referred to as a third regionR3) at an interface between the third semiconductor layer 10 b′ and thebipolar memory element M1. A residue region of the third semiconductorlayer 10 b′ (referred to hereinafter as the fourth region R4), otherthan the third region R3, may have a semiconductor characteristic. Asdescribed above, the first and third semiconductor layers 10 a′ and 10b′ may include the first and third regions R1 and R3 having relativelyhigh electric conductivity, respectively, and may directly contact thebipolar memory element M1 through the first and third regions R1 and R3.Accordingly, an intermediate electrode (e.g., formed of metal, etc.)need not be formed between the first and third semiconductor layers 10a′ and 10 b′ and the bipolar memory element M1.

When the first and third semiconductor layers 10 a′ and 10 b′ are n-typeoxide layers, the first and third regions R1 and R3 having relativelyhigh electric conductivity may have a lower oxygen concentration in thefirst and third semiconductor layers 10 a′ and 10 b′, respectively. Inthis example, the oxygen concentration of the first and third regions R1and R3 may be lower than the oxygen concentration of the second andfourth regions R2 and R4. This is because in the case of an n-typeoxide, generally, lower oxygen concentration leads to higher carrierconcentration, and relatively high electric conductivity. When the firstand third semiconductor layers 10 a′ and 10 b′ are p-type oxide layers,the first and third regions R1 and R3 may have a relatively high oxygenconcentration in the first and third semiconductor layers 10 a′ and 10b′. In this example, the oxygen concentration of the first and thirdregions R1 and R3 may be higher than the oxygen concentration of thesecond and fourth regions R2 and R4. This is because in the case of ap-type oxide, generally, higher oxygen concentration leads to highercarrier concentration, and relatively high electric conductivity.Meanwhile, when the first and third semiconductor layers 10 a′ and 10 b′are non-oxide layers (e.g., silicon-based semiconductor layers), thefirst and third regions R1 and R3 may be regions doped with a relativelyhigh concentration of a conductive impurity (n-type or p-type).

Even in the example embodiments illustrated in FIGS. 8 and 9, thebipolar memory element M1 and the switching element (e.g., pn diodesPN1, PN1′, PN2, and PN2′) may include oxides, and the bipolar memoryelement M1 may directly contact the switching element.

According to at least one other example embodiment, in FIG. 8 at leastone of the semiconductor layers 10 a, 10 b, 20 a, and 20 b may have abipolar memory characteristic. In this case, at least a portion of theswitching element (e.g., the first and second pn diodes PN1 and PN2) mayhave a bipolar memory characteristic, and an additional memory elementneed not be used. An example of this structure is illustrated in FIG.10.

Referring to FIG. 10, a first semiconductor layer 100 having a bipolarmemory characteristic is provided, and second and third semiconductorlayers 200 a and 200 b are disposed on bottom and top surfaces of thefirst semiconductor layer 100. In this example, the semiconductor layer100 is a first conduction type semiconductor layer, whereas the secondand third semiconductor layers 200 a and 200 b are second conductiontype semiconductor layers. If the first semiconductor layer 100 is ap-type semiconductor layer, the second and third semiconductor layers200 a and 200 b are n-type semiconductor layers. If the firstsemiconductor layer 100 is an n-type semiconductor layer, the second andthird semiconductor layers 200 a and 200 b are p-type semiconductorlayers.

When the first semiconductor layer 100 is a p-type semiconductor layer,the first semiconductor layer 100 may include, for example, Ni oxide, Cuoxide, a combination thereof or the like. When the first semiconductorlayer 100 is an n-type semiconductor layer, the first semiconductorlayer 100 may include, for example, at least one oxide selected from thegroup consisting of or including: Ti oxide, Co oxide, Hf oxide, Zroxide, Zn oxide, W oxide, Nb oxide, TiNi oxide, LiNi oxide, Al oxide,InZn oxide, V oxide, SrZr oxide, SrTi oxide, Cr oxide, Fe oxide, Taoxide, PrCaMnO (PCMO), a combination thereof or the like. Thesematerials may have a bipolar memory characteristic, and may form a diodeby connection with a different-type semiconductor layer (e.g., thesecond and third semiconductor layers 200 a and 200 b). The firstsemiconductor layer 100 that is a bipolar memory element may form afirst switching element (e.g., a first pn diode PN1″) together with thesecond semiconductor layer 200 a, and may form a second switchingelement (e.g., a second pn diode PN2″) together with the thirdsemiconductor layer 200 b. Accordingly, the structure of FIG. 10 mayalso be regarded as a structure in which first and second pn diodes PN1″and PN2″ are disposed at opposite sides of the bipolar memory element M1(e.g., the first semiconductor layer 100). The switching direction ofthe first pn diode PN1″ may be opposite to the switching direction ofthe second pn diode PN2.″ The second and third semiconductor layers 200a and 200 b may have a composition (or a physical property) that iscontrolled not to have a bipolar memory characteristic therein. However,according to at least one other example embodiment, at least a portionof the second and third semiconductor layers 200 a and 200 b may alsohave a bipolar memory characteristic.

As in the example embodiment illustrated in FIG. 10, when a portion ofthe switching elements PN1″ and PN2″ is used as a bipolar memory element(e.g., when the bipolar memory element is included in the switchingelements PN1″ and PN2″) the structure of a memory device is moresimplified, and thus, relatively high integration rates may be moreeasily achieved.

Memory cells according to example embodiments show voltage-currentcharacteristics as illustrated in FIG. 11 or FIG. 12. FIGS. 11 and 12are voltage-current graphs represented in a log scale.

Referring to FIG. 11, point (1) and point (2) respectively correspond tofirst and second threshold voltages, whereas point (3) and point (4)respectively correspond to set and reset voltages. Accordingly, a writevoltage is in the vicinity of point (3), and an erase voltage is in thevicinity of point (4). The concepts of the set voltage and reset voltagemay be altered, and the concepts of write and erase of information mayalso be altered. A read voltage is between point (1) and point (3). Aninhibition region is set between point (1) and point (2). The inhibitionregion refers to a voltage range in which other memory cells maintaintheir original states when a given memory cell operates. The inhibitionregion may be regarded as a window for memory operation.

Referring to FIG. 12, a write voltage, a read voltage, an erase voltage,and an inhibition region are similar to those described with referenceto FIG. 11.

FIG. 13 is a perspective view of a memory device including a pluralityof memory cells according to an example embodiment. The memory deviceaccording to at least this example embodiment is a multi-layercross-point resistive memory device.

Referring to FIG. 13, a plurality of first electrodes E10 are disposedin parallel with each other. Each first electrode E10 has a wire shapeand extends in a first direction (e.g., an X axis direction). Aplurality of second electrodes E20 are also disposed in parallel witheach other. Each second electrode E20 also has a wire shape. The secondelectrodes E20 are separated from the first electrodes E10, but crosseach other. In the example embodiment shown in FIG. 13, the secondelectrodes E20 are arranged perpendicular to the first electrodes E10.In this case, the second electrodes E20 extend in a second direction(e.g., a Y axis direction), which is perpendicular to the firstdirection. The extension directions of the first and second electrodesE10 and E20 may be altered, and the shapes of the first and secondelectrodes E10 and E20 may be changed.

The first and second electrodes E10 and E20 may be formed of anelectrode material that is generally used in semiconductor devices, andmay have a single-layered or multi-layered structure. For example, thefirst and second electrodes E10 and E20 may include at least oneselected from the group consisting of or including: Pt, Au, Pd, Ir, Ag,Ni, Al, Mo, Cu, combinations thereof or the like. The first and secondelectrodes E10 and E20 may be formed of the same, substantially the sameor different materials and may have the same, substantially the same ordifferent structures.

In the example embodiment shown in FIG. 13, a first memory cell MC10 isdisposed at each intersection of the first electrodes E10 and the secondelectrodes E20. The first memory cell MC10 may have the same orsubstantially the same structure as that of the memory cell MC1 ofFIG. 1. In more detail, the first memory cell MC10 may include a firstswitching element S10, a first bipolar memory element M10 and a secondswitching element S20, which are sequentially disposed in that order onthe first electrode E10. In this example, the first switching elementS10, the first bipolar memory element M10 and the second switchingelement S20 correspond to the first semiconductor layer 1 a, the bipolarmemory element M1, and the second semiconductor layer 1 b of FIG. 3,respectively. In this regard, the first and second electrodes E10 andE20 correspond to the first and second metal layers 2 a and 2 b of FIG.3, respectively. A first Schottky barrier may be formed between thefirst switching element S10 and the first electrode E10, and a secondSchottky barrier may be formed between the second switching element S20and the second electrode E20.

Alternatively, the first switching element S10, the first bipolar memoryelement M10 and the second switching element S20 may respectivelycorrespond to the first pn diode PN1, the bipolar memory element M1, andthe second pn diode PN2 of FIG. 8. In yet another alternative, the firstswitching element S10, the first bipolar memory element M10 and thesecond switching element S20 may respectively correspond to the first pndiode PN1′, the bipolar memory element M1, and the second pn diode PN2′of FIG. 9.

In yet another example, the first bipolar memory element M10, the firstswitching element S10, and the second switching element S20 mayrespectively correspond to the first semiconductor layer 100, the secondsemiconductor layer 200 a, and the third semiconductor layer 200 b ofFIG. 10.

The materials, structures, and characteristics of the first switchingelement S10, the first bipolar memory element M10, and the secondswitching element S20 have been described with reference to FIGS. 1through 3 and 8 through 10. For example, if the first memory cell MC10has a structure similar to that of the memory cell of FIG. 3, the firstmemory cell MC10 may include oxides of the same group and the oxygenconcentration thereof may vary according to a height direction (e.g., aZ-axis direction). In a more concrete example, the first electrode E10,the first switching element S10, the first bipolar memory element M10,the second switching element S20, and the second electrode E20 may be aPt layer, a TiO_(x) (30%) layer, a TiO_(x) (15%) layer, a TiO_(x) (30%)layer and a Pt layer, respectively. However, the structure of the firstmemory cell MC10 is not limited thereto and may vary as described above.

Still referring to FIG. 13, a plurality of third electrodes E30 aredisposed on top surfaces of the second electrodes E20 and are separatedfrom the second electrodes E20. Each third electrode E30 has a wireshape, and the third electrodes E30 are disposed in parallel with eachother. The third electrodes E30 and the second electrodes E20 also crosseach other. In this example, the third electrodes E30 and the secondelectrodes E20 are arranged perpendicular to each other. A material forforming the third electrodes E30 may be the same or substantially thesame as the material of the first and second electrodes E10 and E20.

A second memory cell MC20 is disposed at each intersection of the secondelectrodes E20 and the third electrodes E30. The second memory cell MC20includes a third switching element S30, a second bipolar memory elementM20 and a fourth switching element S40, which are sequentially disposedon the second electrode E20 in that order. The third switching elementS30, the second bipolar memory element M20 and the fourth switchingelement S40 correspond to the first switching element S10, the firstbipolar memory element M10 and the second switching element S20,respectively. In this example, the second memory cell MC20 and the firstmemory cell MC10 have the same stacked structure. In this regard, thefirst and second memory cells MC10 and MC20 may have the circuitstructure of FIG. 2A or FIG. 2B. The switching direction of the thirdswitching element S30 may be opposite to the switching direction of thefirst switching element S10, and the switching direction of the fourthswitching element S40 may be opposite to the switching direction of thesecond switching element S20. Thus, the third and fourth switchingelements S30 and S40 of the second memory cell MC20 may have switchingdirections opposite to those of the first and second switching elementsS10 and S20 of the first memory cell MC10. In this regard, any one ofthe first and second memory cells MC10 and MC20 may have the circuitstructure of FIG. 2A, and the other memory cell may have the circuitstructure of FIG. 2B.

FIGS. 14A and 14B illustrate example circuit structures, each includingthe first memory cell MC10, the second electrode E20 and the secondmemory cell MC20 of FIG. 13.

Referring to FIG. 14A, each of the first memory cell MC10 and the secondmemory cell MC20 has the circuit structure of FIG. 2A.

The second and third switching elements S20 and S30 located at oppositesides of the second electrode E20 have opposite switching directions. Asa result, information may be simultaneously written to two bipolarmemory elements M10 and M20 using the second electrode E20 as a commonbit line.

Referring to FIG. 14B, the first memory cell MC10 has the circuitstructure of FIG. 2A, but the second memory cell MC20 has the circuitstructure of FIG. 2B. In this example, the second and third switchingelements S20 and S30 located at opposite sides of the second electrodeE20 have the same switching directions, and thus, information may bewritten to any one of the bipolar memory elements M10 and M20 by oneprogramming operation.

In FIG. 13, the first and second memory cells MC10 and MC20 arecylindrical. However, the shapes of the first and second memory cellsMC10 and MC20 are not limited thereto. For example, the first and secondmemory cells MC10 and MC20 may have a square pillar shape or a shapethat has an increasing (or tapered) width (e.g., in the downwarddirection). For example, the first and second memory cells MC10 and MC20extend outward from the intersections of the first and second electrodesE10 and E20 and the intersections of the second and third electrodes E20and E30.

Although not illustrated, the memory device of FIG. 13 may furtherinclude a structure that is the same or substantially the same as thestack structure including the first memory cell MC10 and the secondelectrode E20, on the third electrode E30.

Alternatively, the memory device of FIG. 13 may further include at leastone set of a structure that is the same or substantially the same as thestack structure including the first memory cell MC10, the secondelectrode E20, the second memory cell MC20 and the third electrode E30,on the third electrode E30.

Alternatively, the memory device of FIG. 13 may further include at leastone set of a structure that is the same or substantially the same as thestack structure including the first memory cell MC10, the secondelectrode E20, the second memory cell MC20, the third electrode E30, thefirst memory cell MC10, and the second electrode E20, which aresequentially stacked in that order, on the third electrode E30.

FIG. 15 is a schematic diagram illustrating a memory card according toan example embodiment.

Referring to FIG. 15, a controller 510 and a memory 520 are configuredto exchange electrical signals. For example, the memory 520 and thecontroller 510 are configured to exchange data according to commands ofthe controller 510. The memory card 500 may either store data in thememory 520 or output data from the memory 520. The memory 520 mayinclude one of the non-volatile memory devices described above withreference to FIGS. 1 through 14B.

Such a memory card 500 may be used as a storage medium for variousportable electronic devices. For example, the memory card 500 may be amultimedia card (MMC), a secure digital (SD) card or the like.

FIG. 16 is a block diagram illustrating an electronic system accordingto an example embodiment.

Referring to FIG. 16, a processor 610, an input/output device 630, and amemory 620 perform data communication with each other via a bus 640. Theprocessor 610 is configured to execute a program and control theelectronic system 600. The input/output device 630 is configured toinput/output data to/from the electronic system 600. The electronicsystem 600 may be connected to an external device such as a personalcomputer or a network, by the input/output device 630. The electronicsystem is configured to exchange data with the external device.

The memory 620 is configured to store codes or programs for operatingthe processor 610. The memory 620 may include one of the non-volatilememory devices described above with reference to FIGS. 1 through 14B.

The electronic system 600 may embody various electronic control systemsrequiring or including the memory 620, and may be used in mobile phones,MP3 players, navigation devices, solid state disks (SSD), householdappliances, etc.

Example embodiments are discussed herein with regard to bipolar memoryelements. However, example embodiments may also be applicable tounipolar memory elements. A unipolar memory element differs from abipolar memory element in that the unipolar memory element includes adata storage element that exhibits unipolar switching in whichresistance characteristics or a resistance state of the data storagematerial layer are switchable between two different states (a highresistance state and a low resistance state) using voltages having thesame polarity. In this context, “resistance characteristics” refers to adevice's response to a particular applied voltage. Thus, in having“different resistance characteristics,” the device's response to thesame or substantially the same voltage is different depending on theresistance state of the device. The data storage material layer may be atransition metal oxide layer such as NiO, V₂O₅, ZnO, Nb₂O₅, TiO₂, WO₃,CoO layers, etc.

The example embodiments described herein should be considered in adescriptive sense only and not for purposes of limitation. Descriptionsof features or aspects within each example embodiment should beconsidered as available for other similar features or aspects in otherexample embodiments. For example, it would be obvious to one of ordinaryof ordinary skill in the art that the structures of a, memory devicepresented in the example embodiments described above may be variouslychanged. In more detail, the memory cells illustrated in FIGS. 1, 3, and8 through 10 may be used in various other memory devices, in addition tothe cross-point memory device illustrated in FIG. 13. Moreover, in thememory cells according to example embodiments described above, variousother memory elements, in addition to a resistive memory element, mayalso be used as a bipolar memory element.

1. A memory device comprising a memory cell, the memory cell comprising:a bipolar memory element; and a bidirectional switching elementconnected to ends of the bipolar memory element, the bidirectionalswitching element having a bidirectional switching characteristic. 2.The memory device of claim 1, wherein the bidirectional switchingelement comprises: a first switching element connected to a first end ofthe bipolar memory element and having a first switching direction; and asecond switching element connected to a second end of the bipolar memoryelement and having a second switching direction, which is opposite tothe first switching direction.
 3. The memory device of claim 2, whereinthe first and second switching elements are Schottky diodes.
 4. Thememory device of claim 3, wherein the first switching element includes afirst semiconductor layer and the second switching element includes asecond semiconductor layer, and each of the first and secondsemiconductor layers contact the bipolar memory element, and wherein thebipolar memory element, the first semiconductor layer and the secondsemiconductor layers are oxide layers.
 5. The memory device of claim 4,wherein an oxygen concentration of the bipolar memory element is lowerthan oxygen concentrations of the first and second semiconductor layers.6. The memory device of claim 3; wherein the first switching elementincludes a first electrode contacting a first semiconductor layer, andthe second switching element includes a second electrode contacting asecond semiconductor layer; wherein the first electrode, the firstsemiconductor layer, the bipolar memory element, the secondsemiconductor layer and the second electrode are in the form of a stackstructure.
 7. The memory device of claim 6, wherein the first electrodeand the second electrode are platinum (Pt) layers, the first and secondsemiconductor layers are TiO_(x) (30%) layers, and the bipolar memoryelement is a TiO_(x) (15%) layer.
 8. The memory device of claim 2,wherein the first and second switching elements are pn diodes.
 9. Thememory device of claim 8, wherein the first switching element includes afirst semiconductor layer, and the second switching element includes asecond semiconductor layer, and wherein the first and secondsemiconductor layers contact the bipolar memory element, and aconductive region is formed in a portion of each of the first and secondsemiconductor layers contacting the bipolar memory element.
 10. Thememory device of claim 9, wherein the first and second semiconductorlayers are n-type oxide layers, and the conductive region has a loweroxygen concentration than residue regions of the first and secondsemiconductor layers.
 11. The memory device of claim 9, wherein thefirst and second semiconductor layers are p-type oxide layers, and theconductive region has a higher oxygen concentration than residue regionsof the first and second semiconductor layers.
 12. The memory device ofclaim 8, wherein the bipolar memory element is formed of an oxide. 13.The memory device of claim 2, wherein at least a part of the bipolarmemory element forms a part of the first and second switching elements.14. The memory device of claim 13, wherein the memory cell furthercomprises: a first semiconductor layer having a first conduction type;and second and third semiconductor layers having a second conductiontype disposed at ends of the first semiconductor layer; wherein thefirst semiconductor layer is the bipolar memory element, the firstsemiconductor layer and the second semiconductor layer form the firstswitching element, and the first semiconductor layer and the thirdsemiconductor layer form the second switching element.
 15. The memorydevice of claim 2, wherein the bipolar memory element includes an oxideresistor.
 16. The memory device of claim 15, wherein the oxide resistorincludes at least one material selected from the group including Tioxide, Ni oxide, Cu oxide, Co oxide, Hf oxide, Zr oxide, Zn oxide, Woxide, Nb oxide, TiNi oxide, LiNi oxide, Al oxide, InZn oxide, V oxide,SrZr oxide, SrTi oxide, Cr oxide, Fe oxide, Ta oxide, and PCMO(PrCaMnO).
 17. The memory device of claim 15, wherein each of the firstand second switching elements includes an oxide semiconductor.
 18. Thememory device of claim 17, wherein the oxide semiconductor includes anoxide of the same group as the oxide resistor.
 19. The memory device ofclaim 17, wherein the oxide semiconductor includes an oxide of adifferent group from the oxide resistor.
 20. The memory device of claim17, wherein the oxygen concentration of at least a portion of thebipolar memory element is different from the oxygen concentration of atleast a portion of the first and second switching elements.
 21. Thememory device of claim 2, wherein each of the first and second switchingelements includes an oxide semiconductor.
 22. The memory device of claim2, wherein a doping condition of at least a portion of the bipolarmemory element is different from a doping condition of at least aportion of the first and second switching elements.
 23. The memorydevice of claim 2, wherein the first and second switching elementsdirectly contact ends of the bipolar memory element.
 24. The memorydevice of claim 2, wherein the memory cell is an oxide unit.
 25. Thememory device of claim 2, further comprising: a plurality of firstelectrodes having a wire shape, the plurality of first electrodes beingdisposed in parallel with each other; and a plurality of secondelectrodes having a wire shape, the plurality of second electrodes beingdisposed in parallel with each other; wherein the memory cell isdisposed at each of the intersections of the first and secondelectrodes.
 26. The memory device of claim 25, wherein the memory cellis a first memory cell, and the memory device further comprises: aplurality of third electrodes crossing the second electrodes, theplurality of third electrodes having a wire shape, and, being inparallel with each other; and a second memory cell disposed at each ofthe intersections of the second and third electrodes.
 27. The memorydevice of claim 26, wherein the second memory cell and the first memorycell have a same structure.
 28. The memory device of claim 26, whereinthe second memory cell has a modified structure from the first memorycell in which the switching directions of first and second switchingelements are inversed.
 29. A memory card comprising: a controller; and amemory including the memory device of claim 1, the memory beingconfigured to exchange data with the controller according to commandsfrom the controller.
 30. An electronic device comprising: a processorconfigured to control the electronic device; an input/output deviceconfigured to input/output data to/from the electronic device; and amemory including the memory device of claim 1, the memory beingconfigured to store at least one of codes and programs for operating theprocessor; wherein the processor, the input/output device and the memoryare configured to exchange data via a bus.